About
The Analog Decoding Workshop began in 2002, and continues as an annual international meeting of researchers in areas related to analog iterative decoding. In its strictest sense, “Analog Decoding” refers primarily to the family of low-power analog computation circuits that can be used to implement error-correcting algorithms for communication and storage systems. These algorithms include Turbo codes, Low-Density Parity-Check (LDPC) codes, trellis codes and others.
The Analog Decoding Workshop has steadily expanded to include non-traditional or analog-like decoding approach, such as stochastic arithmetic and bit-flipping algorithms. The workshop has also provided a forum for broader topics in communications and electronics. Past topics included:
- Factor graph methods for ADC calibration.
- Analog decoding in computational bio-sensors.
- Binary differential decoding of LDPC codes.
- Power analysis and optimization of conventional decoders and communication systems.
- Architectures and algorithms for next-generation wireless networks.
The workshop is also open to presentations from researchers in related areas which might contribute to collaboration or future directions in analog decoding research.